1. Technical Field of the Invention
The present invention relates to an interface system that includes delay circuitry to delay a non-periodic strobe signal between electrical components and, more particularly, to such an interface system in which the delay circuitry includes DC level restoration to prevent pattern dependent jitter.
2. Background Art
Data is often transferred between two electrical components. For example, data is transferred between a microprocessor and memory. In what is referred to as a common clock paradigm, signals from a clock are supplied to both the sending and receiving component. Data is transferred from the sending component and latched in the receiving component within one clock cycle. Accordingly, the rate at which data can be transferred between components is limited by the flight time of the data across the conductors. Above a certain level of clock frequency, the common clock methods can no longer be used because the electrical length of the interconnect becomes longer than a clock period.
To overcome the problem, techniques have been developed in which timing information is transmitted with the data in order to latch it at the receiving side of a link. This is referred to as source synchronous signaling. Under one technique, timing information is transmitted on the same conductor as the data. Under a second technique, timing information is transmitted over a separate conductor.
Under one approach of the second technique, a differential timing signal or strobe toggles only when data is being transmitted on the link between components. The data is latched at the receiving side of the link. A circuit translates the latched data to the receiving component's clock domain. The strobe signal is offset from the data to center the strobe with respect to the data cell. A series of resistor capacitor loaded inverters have been used in delay circuits. Providing an accurate delay is complicated by the strobe signal being non-periodic. By non-periodic, it is meant that the strobe signal toggles only in connection with transfer of data. (However, the strobe signal may be periodic within temporal boundaries.) Accordingly, the timing information is available only intermittently. Also, nodes of delay circuitry have a bandwidth greater than the frequency of the incoming data. If this condition is not met, the voltage of the nodes in the delay circuitry may become data pattern dependent. For a clock pattern, the voltages of the nodes do not reach the rails, whereas for long strings of ones and zeros, the voltages do, leading to pattern dependent jitter of the timing signals.
Accordingly, there is a need for an interface system that avoids pattern dependent jitter in delaying non-periodic timing signals.